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Tekedia Preliminary Review of Google Chromebook

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We have a copy of the Google Chromebook.  It is the Samsung Series 5 Chromebook. The first thing is that there is no desktop. It is browser-top. It uses Chrome web browser and of course the OS is Chrome. This is nothing but a thin client or zero client where they make you to emulate your screen while your data is resident in a server somewhere. A Google staffer who has one gave it to us last night to play with. We will buy one from Amazon tomorrow when it officially releases.

 

It has all the usual features in a typical notebook- the display, the battery, Atom processor and 2GB Memory with SSD of 16GB.

 

According to Google, Chromebooks are built and optimized for the web, where you already spend most of your computing time. So you get a faster, simpler and more secure experience without all the headaches of ordinary computers.

 

To us, this is a notebook without the usual hard drive.  They want you to migrate from the standalone PC to something that is connected in a cloud with all storage services in the cloud.

 

True, Chrome books up in 8 seconds. It ramps up to the web either through Wi-Fi or 3G. The cool stuff is that the images look sharp. All data is in the cloud. No HDD. You need to get use to this monster because all those My Computer are history. We like the 12.1 inch LCD. It looks very nice.  Setting it at 1280 by 800, the stuff comes out cleanly and nice.

 

We are working on a full post which will be up this weekend when we can spend more time with Chromebook. We are getting one.  Time was not enough to get all the facts, but the coolest part of this machine is that it is up in 8 seconds. That is the innovation.

 

The major weakness we have seen in Chromebook is the fact that developing nations could suffer. Most of the applications need Internet connection. Maybe Google has to figure out a way to make them tank when not online.

 

No judgement and over the weekend we will compare Chromebook with PC. Check Tekedia over the weekend and you will see Tekedia Chromebook in action.

Nigeria 2011 S&T Budget Is Less Than Microsoft R&D Weekly Tab. A Senator Spends Monthly What Some Agencies Spend Annually

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We will be analyzing the science and technology budget of the Federal Ministry of Science and Technology.  The budget is available here:

 

People, we are still far below. What Microsoft spends on R&D in a week covers what Nigeria budgets for the science and technology ministry.At around $9.5 billion, Microsoft puts more than in N1 trillion in R&D. One percent of that is about N10 billion. Alternatively, look at it from weekly R&D money. Let us say $19 billion per  week for Microsoft – that is what the numbers work out to be. The total budget in the S&T Nigeria is not up to that weekly figure.

 

It is just unfortunate. We will be looking at the numbers closely and telling you what we expect in the agencies. The money is small because the salaries are eating the figures. Tekedia is at work and we are looking at them..

 

Key immediate numbers are:

NATIONAL INFORMATION TECHNOLOGY DEVELOPMENT AGENCY (NITDA) gets only N6.5m for total capital

 

The big guy is NATIONAL SPACE RESEARCH AND DEVELOPMENT AGENCY – ABUJA which gets N730,165,405 for capital cost

 

But you know what? One Senator spends, monthly, what some of these agencies spend in year. Who is deceiving who?

Power Dissipation and Interconnect Roadmap

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Since the invention of integrated circuits by Jack Kilby few decades ago, the number of transistors in a die has continuously doubled every 24 months. This is the famous Moore’s law, which is still relevant today. Sustaining this trend has been fuelled by the abilities of the chip designers to cramp more transistors together. As noted above, it has made the designs denser but has introduced problems like power dissipations and interconnects noise. From many indications, the CMOS technology remains the most elegant technology for making chips owing to its low power static dissipation and ease of integration when compared with technology like bipolar junction transistors (BJT). This implies that it would be in use in the foreseeable future and battling the associated problems provides a huge challenge to the stakeholders.

 

State of the art CMOS technologies are well below 100-nanometer transistor feature size. Products made based on 65-nanometer process have already hit the market. 45-nanometer and 32-nanometer CMOS processes are expected before 2008 and 2010 respectively. This ambitious strategy of transistor miniaturization translates to making interconnects that are thinner as well as scaling the system supply power.

 

To make these systems appealing to the customers, there are tight budgets in power consumption and other parameters. For instance, the ITRS (2005) forecasts an allowable maximum power for battery (low cost/handheld) operated systems of 2.8W in 2005 to only 3W in 2020 [This is a very tight budget considering the expected advancements and complexities in these systems].

 

Within this period, the power supply for high performance systems is expected to scale down by 36% while the allowable maximum power for high performance (with heatsink) devices will increase by only 19%. The underlining consequence of this scaling would be more dominant short channel effects (SCE) and gate leakage current partly due to shorter features sizes and thinner gate oxide thickness respectively. Besides, problems associated with controlling the threshold voltage as a result of non-uniform doping as technology scales will be a major issue.

 

Similarly, the effect of feature size reduction affects the interconnect performance. The decrease in interconnection width and thickness increases resistance while smaller spacing progressively increases the circuit capacitance. This increase in resistance and capacitance are not desirable in the chip wires. These effects have resulted to increased role of interconnect in integrated circuit design and development. As the fringing field component of wire capacitance does not vary with feature size, when the three wire dimensions are scaled by the same scaling factor, the interconnect delay is not affected. But in reality, the scalings of the wire dimensions are not unified by the same scale factor.

 

Furthermore, by packing more circuits on a single die made possible by the smaller sizes of the transistors, the numbers of long interconnections are significantly increased. The resulting effect is that the interconnect delay grows bigger and even more than the gate delay of the transistor. With continuous reduction in the feature size, interconnect noise and delay will continue to be a major issue. Aluminum, once the main material for interconnect has long been replaced by copper, which has a lower resistivity. But with time, the performance of copper/low-k interconnects will become inadequate to meet the speed and power dissipation goals of highly scaled ICs.

 

So what is the future? The ITRS proposes an early availability of high-k gate dielectrics in order to meet the stringent gate leakage especially in low power devices. It also stated that development of low dielectric constant (low-?) material together with low-resistivity metal system would become critical for signal propagation delay reduction. Nonetheless, it acknowledges that accessing the road map is a ‘red brick’, i.e. ‘no known solution’ at least within this decade. In many instances, nanotechnology has been projected to supersede CMOS technology unless the challenges are overcome.

 

Notwithstanding, the challenges of interconnect and power dissipation calls for new system architecture, new materials and innovative optimization tools that would help to accurately model the complex relationships that exist in the system at nanometer regime. The chip makers have vigorously used new materials to reduce interconnect capacitance ( eg, Intel has used low-k carbon doped oxide dielectric to obtain lower interconnect capacitance) in their newer processes. Aggressive new trends would certainly emerge in the future if the demise of Moore’s law should be delayed

Electronic Commerce in Nigeria is Making Progress

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The landscape of the ecommerce in Nigeria has long been cemented. Gone were the days when nothing could happen online. But all that has changed.  The nation is making progress and very quick.

 

Tekedia notes that there are many Nigerian sites with full e-commerce capabilities these days with payment method denominated with Naira. In other words, they have built methods for those that operate electronic payments in Naira to participate. This industry is growing and very healthy indeed.

 

With more Nigerians online now, this business will surely improve. In most statistics, including Facebook and other top websites Nigerians are getting online and that is good news for the growth of the mobile and electronic payment. The more time they spend online, the more they will shop online.

 

With some kind of standards and unification in the payment system, there is now a big order.  Interswitch is the behemoth while etranzact works the line. Nearly all the banks have Interswitch readiness.  Having that consortium is already helping the ecosystem. The good news is that the card which is used in Nigeria could be used as in other nations – POS, Internet, ATM. Of course, not many will use their cards online because of the illusion of risk.

 

For some big websites, we have noted direct logo of international brands like Visa and Mastercard. The banks are using these cards in the country.  Though Paypal are integrated in some sites, but the banks are not local and that does not help that much.

 

The big change will come with the penetration of mobile payment. As the players juggle with their licenses, mobile and epayment in Nigeria will grow.

 

The major drawback to the faster adoption of eCommerce remains the cost of  integrating Interswitch. It is very expensive with more than N150,000 just to set it up per site. With that kind of money, people will not go in a hurry to have that included.

Power Dissipation and Noise Challenges in Ultra Deep Submicron CMOS Technology

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The invention of complementary metal oxide semiconductor (CMOS) integrated circuit is a major milestone in the history of modern industry and commerce. It has driven revolutionary changes in computing due to its performance, cost and ease of integration. But as the size of the transistors scale down into the nanometer regime, so many challenges occur on the reliability and performance of the systems.

 

Signal integrity and power problems are noticeably among the major ones. In the past few decades, the advancement of the chip performance has come through increased integration and complexity on the number of transistors on a die. Though supply and threshold voltages have been scaled for every CMOS generation, the power dissipation and interconnect noise have continued to increase. This trend is costly in terms of shorter battery life, complex cooling and packaging methods, and degradation of system performance.

 

Power dissipation in CMOS circuits involves both static and dynamic power dissipations. In the submicron technologies, the static power dissipation, caused by leakage currents and subthreshold currents contribute a small percentage to the total power consumption, while the dynamic power dissipation, resulting from charging and discharging of parasitic capacitive loads of interconnects and devices dominates the overall power consumption.

 

But as technologies scale down to the nanometer regime (ultra deep submicron (UDSM)), the static power dissipation becomes more dominant than the dynamic power consumption. And despite the aggressive downscaling of device dimensions and reductions of supply voltages, which reduce the power consumption of the individual transistors, the exponential increase of operating frequencies results in a steady increase of the total power consumption.

 

Interconnect noise and delay emanate during distribution of on chip signals and clocks using local, intermediate and global wires. Introduction of repeaters on the interconnect paths mitigate the effect of delay at the expense of chip area and power consumption. With technology downscaling, interconnect resistance and capacitance increases the propagation delay. As the cross section of chip interconnect is reduced, the resistance per unit length is increased. Closer routing and wire reduction have increased chip interconnect capacitance and resistance effects respectively.

 

The relationships between interconnect delay and technology show that downscaling of feature size increases circuit propagation delay. It is evident that as the technology scales, the gate delay decreases but with increase in interconnect delay. At around 0.12um technology, the interconnect delay has become exceedingly dominant over the gate delay. This increase is worrisome to chip designers in the quest for continuous circuit miniaturization and denser integration in CMOS technology.

 

The International Technology Roadmap for Semiconductor (ITRS) 2005 forecasts continuous reduction in feature size to be alive and well into the future. With this continuous scaling, if interconnect noise and power dissipation, especially the static power dissipation, are not controlled and optimised, they promise to become major limiting factors for system integration and performance improvement.