17 Technical Citations On Our Journal Article Predicting The Challenges Of Ultra Deep Submicron CMOS Technologies

This piece was written in 2006 and was well received in the technical community. It has been been published in IEEE Potentials. In it, we predicted the challenges of the ultra deep submicron CMOS technologies. Then we offered roadmaps to solving them. We just checked today; 17 people have cited it. Notice that due to how Google Scholar works, there are usually more citations than recorded. A single mistake in the title or the way the name is written will throw Google algorithms into limbo. But even the 17 is not bad. To get cited in a technical journal is not a piece of cake or ice cream. This is the original paper in case you want to read. In it, we modeled the transistor down to the 64nm CMOS when it was just coming. In short, this work was one of the earliest to have done it.

 

Power dissipation sources and possible control techniques in ultra deep submicron CMOS technologies

[PDF] from afrit.org N Ekekwe… – Microelectronics journal, 2006 – Elsevier
As technology scales down into the ultra deep-submicron (UDSM) region, the static power dissipations
grow exponentially and become an increasingly dominant component of the total power dissipation
in CMOS circuits. With increase in gate leakage current resulting from thinner gate oxides
Cited by 17Related articlesAll 5 versions
Scholar     Create email alert Results 110 of about 17. (0.08 sec)

Power-aware real-time scheduling upon identical multiprocessor platforms

[PDF] from psu.eduV Nélis, J Goossens, R Devillers… – … Conference on Sensor …, 2008 – computer.org
In this paper, we address the power-aware scheduling of sporadic constrained-deadline hard
real-time tasks us- ing dynamic voltage scaling upon multiprocessor platforms. We propose two
distinct algorithms. Our first algorithm is an off-line speed determination mechanism which
Cited by 5Related articlesAll 19 versions

A 5-bits precision CMOS bandgap reference with on-chip bi-directional resistance trimming

N Ekekwe… – Circuits and Systems, 2008 …, 2008 – ieeexplore.ieee.org
Ndubuisi Ekekwe, Ralph Etienne-Cummings Department of Electrical & Computer Engineering
Johns Hopkins University Baltimore, MD, USA {nekekwe1, retienne} @jhu.edu Abstract—This
paper presents the design and implementation of a high precision CMOS bandgap
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Power-Aware Real-Time Scheduling upon Dual CPU Type Multiprocessor Platforms

[PDF] from ulb.ac.beJ Goossens, D Milojevic… – Principles of Distributed Systems, 2008 – Springer
Abstract. Nowadays, most of the energy-aware real-time scheduling al- gorithms belong to the
DVFS (Dynamic Voltage and Frequency Scaling) framework. These DVFS algorithms are usually
efficient but, in addition to often consider unrealistic assumptions: they do not take into
Cited by 1Related articlesAll 11 versions

Power Dissipation Associated to Internal Effect Transitions in Static CMOS Gates

[PDF] from us.esA Millan, J Juan, M Bellido, D Guerrero… – Integrated Circuit and …, 2009 – Springer
Power consumption has become a key issue in UDSM technologies (0.25 ?m and lower
[1][2]) due to an increasing demand for portable battery-powered appli- ances and the durability
and reliability problems associated with the high power densities, which need to be
Cited by 1Related articlesAll 3 versions

Integrated silicon waveguide for intra-chip communication: A practical experience

N Ekekwe – … , 2007 International Students and Young Scientists …, 2007 – ieeexplore.ieee.org
I. INTRODUCTION Advances in technology applications have brought a need for faster computing
performance. Through continuous transistor scaling, this speed has consistently increased in
the last four decades. With increase in interconnect delay, power dissipation and
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[HTML] Novel Circuit Technique for Reduction of Leakage Current in Series/Parallel PMOS/NMOS Transistor Stack

[HTML] from ietejournals.orgV Neema, SS Chouhan… – IETE Journal of Research, 2010 – jr.ietejournals.org
Stacking of MOS transistors is used for minimization of leakage current in nano-scale Complementary
Metal Oxide Semiconductor (CMOS) circuits. Stack arrangement of P-Channel Metal Oxide Semiconductor
(PMOS) is preferred over N-Channel Metal Oxide Semiconductor (NMOS) because value
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A Millan, J Juan, MJ Bellido… – Integrated circuit and …, 2009 – books.google.com
Power Dissipation Associated to Internal E?ect Transitions in Static CMOS Gates Alejandro
Millan, Jorge Juan, Manuel J. Bellido, David Guerrero, Paulino Ruiz-de-Clavijo, and Julian Viejo
Grupo ID2 (Investigacion y Desarrollo Digital) ETSI Informatica (Tec. Electronica)
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P López, J Hauer, B Blanco-Filgueira… – Solid-State Electronics, 2009 – Elsevier
The impact of the layout style on the performance of CMOS circuits and devices is a well-known
fact with maximum relevance on the design of radiation-tolerant devices. Using conventional
transistors, positive charge trapping that accumulates in the oxide bordering the transistor
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V Neema, S Chouhan… – Proceedings of the International …, 2010 – portal.acm.org
INTRODUCTION Active drain current is the current that flows from VDD when the transistor is
in ‘ON’ state[2]. This current is contributing for the output logic levels as well as main cause of
power dissipation [1]. When the circuit is in active mode due to drain current two types of
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M Kumar, S Pandey… – High Performance Architecture and Grid …, 2011 – Springer
A. Mantri et al. (Eds.): HPAGC 2011, CCIS 169, pp. 159–168, 2011. © Springer-Verlag Berlin
Heidelberg 2011 Design of CMOS Energy Efficient Single Bit Full Adders Manoj
Kumar1, Sujata Pandey2, and Sandeep K. Arya1 1 Department of Electronics &
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[HTML] from hindawi.comD Subhra, P Manisha… – VLSI Design, 2011 – hindawi.com
In recent years, the demand for power sensitive designs has grown significantly due to the fast
growth of battery-operated portable applications. As the technology scaling continues
unabated, subthreshold device design has gained a lot of attention due to the low-power
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N Chabini… – Multimedia Computing and Systems (ICMCS … – ieeexplore.ieee.org
Abstract — For CMOS-based nanometer technology, leakage power dissipation became an
important issue in low power design. An approach to deal with this problem for timing constrained
digital designs is to use dual threshold voltages. A low threshold voltage is used for

[PDF] from hindawi.comS Dhar, M Pattanaik… – 2011 – downloads.hindawi.com
Hindawi Publishing Corporation VLSI Design Volume 2011, Article ID 178516, 19 pages
doi:10.1155/2011/178516 Advancement in Nanoscale CMOS Device Design En Route to
Subhra Dhar,1 Manisha Pattanaik,1 and Poolla Rajaram2
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[PDF] Asynchronous Digital Design in Nanometer CMOS Microelectronics Education

[PDF] from eda-publishing.orgN Ekekwe… – eda-publishing.org
ABSTRACT The invention of complementary metal oxide semiconductor (CMOS) technology
has revolutionized the modern industry. But as it scales into the nanometer regime; it faces numerous
challenges on performance and reliability owing to increased interconnect noise, power
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[PDF] from ajol.infoM Kumar, SK Arya… – International Journal of Engineering, Science – ajol.info
Page 1. MultiCraft International Journal of Engineering, Science and Technology Vol. 2, No. 6,
2010, pp. 297-305 INTERNATIONAL JOURNAL OF ENGINEERING, SCIENCE AND
TECHNOLOGY www.ijest-ng.com © 2010 MultiCraft Limited. All rights reserved
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V Neema, SS Chouhan… – Electronic Devices, Systems and … – ieeexplore.ieee.org
Abstract— Stacking of MOS transistors [1] is used for minimization of standby current in
Nano-scale CMOS circuits. Stacking of PMOS is preferred over NMOS because value of active
drain current in PMOS is less than NMOS. It results because of mobility of holes in PMOS
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[PDF] from ijest.infoP MISHRA, HN Shankar, RR Shetty… – International Journal of …, 2010 – ijest.info
Abstract: In this paper, we characterize novel architectures for low power and enhanced performance
of multi-bit encoded booth multipliers. The proposed architectures aim at reducing the switching
activity and the critical path delay to improve the performance of the multiplier. We
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