The global race to build artificial intelligence infrastructure is driving billions of dollars into advanced semiconductor packaging, transforming a once-overlooked stage of chip manufacturing into one of the industry’s most critical production bottlenecks.
As demand for powerful AI processors outpaces available packaging capacity, Nvidia, AMD, and other chip designers are turning to suppliers across Taiwan to secure production, while semiconductor equipment manufacturers accelerate the development of tools for more complex chip assembly.
The investment surge signals a fundamental change in how high-performance processors are manufactured. Rather than relying on a single piece of silicon to deliver greater computing power, chip designers are increasingly combining multiple processors, memory components and other silicon elements into a single package.
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This approach allows components to exchange data more quickly, an important requirement for AI systems that must process enormous volumes of information when training and running large models.
“Packaging was always that thing that you just didn’t worry about,” former Intel chief executive Pat Gelsinger, now a partner at Playground Global, told reporters in Taipei.
That perception is changing as advances in traditional chip miniaturization become harder and more expensive to achieve. Packaging is increasingly determining how much performance manufacturers can extract from processors, particularly as some graphics processing units and central processing units incorporate more than 10 chips, and sometimes as many as 20, in a single package.
Gelsinger estimated that advanced packaging could eventually account for as much as half the value of a chip product.
Research firm Yole Group forecasts that revenue from advanced packaging will exceed revenue from traditional packaging for the first time in 2026. Capital spending on the technology is expected to approach $28 billion, highlighting the scale of investment required to support the next generation of AI hardware.
TSMC’s Dominance Creates Opportunities for Rival Suppliers
Taiwan Semiconductor Manufacturing Company (TSMC), the world’s largest contract chipmaker, dominates the most sophisticated segment of advanced packaging through its chip-on-wafer-on-substrate technology, known as CoWoS.
The process connects separate pieces of silicon, including processors and memory chips, on a shared base, allowing them to operate together at high speed. It has become central to the production of advanced AI processors used by Nvidia, AMD and Broadcom, as well as custom chips developed by major cloud computing companies.
However, constraints on TSMC’s available capacity are pushing chip designers to secure additional production from other suppliers.
Nvidia is providing billions of dollars in financing to expand CoWoS packaging capacity at Siliconware Precision Industries (SPIL), a subsidiary of Taiwan’s ASE Technology, according to an industry executive familiar with the arrangement who spoke to Reuters on condition of anonymity.
The financing will support additional factory space and equipment. The scale of Nvidia’s support had not previously been reported.
The arrangement denotes how competition for advanced packaging capacity is becoming a supply-chain issue for major AI chip developers. Securing access to advanced processors is no longer sufficient if manufacturers cannot obtain the specialized facilities needed to assemble the components into finished products.
The growing importance of packaging also creates opportunities for smaller Taiwanese suppliers seeking to reduce the industry’s dependence on TSMC.
Powertech Technology, also known as PTI, is developing panel-level packaging as an alternative to conventional wafer-based processes. Instead of using round silicon wafers as the packaging platform, the technology uses larger rectangular panels, potentially allowing manufacturers to process more chips in each production run while reducing material waste.
That could become more valuable as AI processors grow larger and their packaging requirements become more complex.
“Everyone is looking for a solution outside TSMC,” PTI Chairman D.K. Tsai told reporters in August. “They don’t want to rely entirely on TSMC.”
PTI is working with AMD and Broadcom to develop the technology for larger chip packages used in AI and high-performance computing. Its senior vice president, Jim Lin, said customers were waiting for the company to increase production capacity.
“The most important thing right now is capacity,” Lin said.
PTI plans to invest $400 million in an advanced packaging joint venture with Broadcom in Singapore, with production potentially beginning in 2028, Tsai said.
TSMC is also developing a panel-based process, chip-on-panel-on-substrate, or CoPoS, to accommodate larger and more complex packages. The company said in April that it had established a pilot production line and expected manufacturing to begin within a couple of years. CoWoS, however, remains its principal technology for AI packaging.
AMD is also expanding its involvement in Taiwan’s semiconductor supply chain, announcing investments of more than $10 billion across the industry, including partnerships with ASE, SPIL and PTI focused on advanced packaging.
AMD Chief Executive Lisa Su acknowledged the need for additional capacity when asked about the industry’s reliance on TSMC.
“I think CoWoS and advanced packaging are super important for our high-performance computing going forward,” Su told Reuters in Taipei in October.
“TSMC has been an incredible partner in advanced packaging, and we’re going to continue to do more together. And yes, we do need more capacity overall.”
Microsoft Azure hardware chief Rani Borkar also identified potential advantages in panel-level packaging, particularly its ability to reduce material waste when assembling larger AI chips. Microsoft has not decided whether or when it will adopt the technology.
Equipment Manufacturers Position for a New Growth Market
The expansion is creating another opportunity for semiconductor equipment manufacturers, whose traditional business has focused on the earlier stages of chip production, when intricate electronic circuits are built onto silicon wafers.
Advanced packaging takes place later in the manufacturing process, joining processors, memory and other components into a finished high-performance unit. As packaging becomes more complex, manufacturers need specialized equipment capable of handling larger structures and more demanding assembly requirements.
Tokyo Electron Taiwan President Seiji Nakama said advanced packaging was growing considerably faster than the broader market for semiconductor manufacturing equipment, although it remained a smaller segment.
An official at US equipment manufacturer Applied Materials said the market for advanced packaging, including panel-level technology, could expand significantly over the next three to five years.
“It’s near-term,” said Sree Kesapragada, a vice president at Applied Materials, which is increasing its focus on the emerging format. “It’s not like, 10 years, 15 years off.”
The shift is creating a new investment cycle across the semiconductor industry. Chip designers need more packaging capacity to meet AI demand, manufacturers are seeking alternatives to existing production constraints, and equipment suppliers are developing the machinery required to support larger and more sophisticated packages.
The economics of AI hardware will continue to depend on this stage of production. As processors become more complex, the ability to integrate multiple chips efficiently could determine how quickly manufacturers deliver new computing capacity and how much performance they can achieve from each generation of silicon.