China’s technology battle with the United States may be entering a new phase after Huawei Technologies unveiled a chip design strategy that seeks to bypass one of the biggest obstacles created by U.S. export restrictions: the inability to access the world’s most advanced semiconductor manufacturing tools.
According to Reuters, rather than continuing the traditional semiconductor industry pursuit of ever-smaller chips, Huawei is proposing a different path built around boosting transmission speed and reducing signal delays across computing systems, an approach the company calls the “Tau Scaling Law.”
The strategy marks one of the clearest signs yet that Chinese technology firms are attempting to develop alternative semiconductor architectures as sanctions increasingly block access to advanced Western chipmaking technology.
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Huawei centers its proposal on a technique known as “LogicFolding,” which seeks to reorganize how circuits are structured inside chips. Instead of relying primarily on shrinking transistor sizes through more advanced manufacturing nodes, Huawei wants to stack logic, memory, and analogue circuits in denser and more tightly connected layers to improve efficiency, computing speed, and power consumption.
The approach is designed to address two converging realities reshaping the semiconductor industry.
The first is a broader technological challenge facing the global chip sector: the slowing pace of Moore’s Law, the decades-old principle that transistor density on chips doubles roughly every two years.
The second is geopolitical.
Since 2019, the United States has progressively tightened restrictions on China’s access to advanced semiconductors and chipmaking equipment. Dutch semiconductor equipment giant ASML Holding has been barred from exporting its most advanced extreme ultraviolet lithography systems to China, preventing Chinese foundries from fully matching cutting-edge manufacturing capabilities at rivals such as Taiwan Semiconductor Manufacturing Company.
Huawei executives now argue that those sanctions forced China to confront semiconductor bottlenecks earlier than the rest of the industry.
“For Huawei, chips face two key constraints,” He Tingbo, president of Huawei’s semiconductor business, told China’s People’s Daily. “One is inevitable that Moore’s Law will hit a physical wall within the next decade. The other is accidental because of the external restrictions that Huawei encountered this wall earlier than its peers.”
While this move is an indication that Chinese firms view U.S. sanctions not merely as a short-term obstacle, but as a catalyst for pursuing a parallel technological roadmap, Huawei’s latest strategy also reflects the changing economics of artificial intelligence computing. As AI models grow larger and more complex, performance bottlenecks are increasingly tied not just to raw transistor density, but to how quickly data moves between processors, memory, and interconnected computing systems.
Reducing latency and improving bandwidth efficiency have therefore become central to next-generation AI infrastructure. That shift has already pushed the broader semiconductor industry toward advanced packaging and three-dimensional chip stacking technologies.
TSMC has spent years developing SoIC packaging technologies that vertically integrate chiplets for better performance and efficiency. South Korean memory giants SK Hynix and Samsung Electronics already use sophisticated 3D stacking methods in high-bandwidth memory chips critical to AI systems.
Even NVIDIA CEO Jensen Huang sought to temper expectations around Huawei’s announcement, arguing that many elements resemble technologies already in commercial use elsewhere.
“This is a breakthrough for Huawei, but it’s not a threat for TSMC,” Huang said in Taipei. “TSMC has been using die stacking and 3D packaging for how long now? Almost 10 years.”
Still, Huawei claims LogicFolding extends beyond conventional stacking by splitting critical logic pathways across multiple layers in ways that could materially improve chip density and clock speeds. The company’s chief semiconductor scientist, Liao Heng, said the architecture enables “very finely and carefully split critical paths of logic circuits across multiple layers,” suggesting Huawei sees the technique as more than incremental packaging refinement.
Analysts, however, say substantial hurdles remain before Huawei can prove the concept at scale.
Research firm Bernstein warned that stacking multiple chip layers increases heat concentration and power density, potentially creating severe thermal management problems. Semiconductor yields and production costs could also become major barriers, especially if manufacturing complexity rises significantly.
Huawei itself acknowledged those challenges.
The company said new electronic design automation tools will likely be needed to optimize folded architectures, while thermal management systems must improve substantially for applications ranging from smartphones to AI data centers.
That presents another challenge because the global EDA software market remains dominated by U.S. firms such as Cadence Design Systems and Synopsys, both central to advanced semiconductor design workflows.
Handel Jones, chief executive of International Business Strategies, said Huawei’s methodology could significantly reshape requirements for semiconductor design software vendors by shifting optimization priorities from chip-level efficiency toward broader system-level timing and performance coordination.
The first major test of Huawei’s claims will likely come later this year when the company launches a new Kirin smartphone processor based on LogicFolding architecture. Huawei said the chip could improve power efficiency by 41% and increase peak operating speeds by nearly 13% compared with its earlier single-layer designs.
If independently verified, those gains would be notable, particularly given China’s restricted access to advanced fabrication technologies.
But analysts caution that Huawei has yet to provide production yield data, manufacturing costs, or benchmark comparisons against competing chips built using leading-edge process nodes.
“There’s nothing concrete that can be independently verified or benchmarked against other players at the moment,” said Lian Jye Su, chief analyst at research firm Omdia.
The announcement nonetheless signals a deeper shift underway in the global semiconductor race. Chinese firms increasingly appear focused on finding architectural and system-level alternatives that reduce dependence on technologies constrained by U.S. sanctions, rather than attempting solely to replicate Western manufacturing progress.
That could gradually produce a more fragmented semiconductor ecosystem, where Chinese and Western companies pursue diverging design philosophies, supply chains, and technology standards.