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Noise Sources And Reduction Techniques In Nanometer CMOS

Noise Sources And Reduction Techniques In Nanometer CMOS

When wires are routed tightly together as is evident in nanometer CMOS technologies, different undesirable effects occur. One is capacitive property formed on the wires resulting from storing charges in the metal interface with oxide. Another is inductive noise resulting from induced voltage on a signal line due to changing magnetic field created when a signal switching causes current to flow through a loop.

By changing signal level and causing oscillatory transitions which could cause overshoot or undershoot, these effects affect circuit performance. These effects are classified as interconnect noise because they emanate from interconnection wires used to link circuit elements on-chip. This noise has resistive, inductive and capacitive components.

Interconnect noise is a huge problem to ultra deep submicron circuit designers because of unwanted variations in signals that degrade system performances. This noise could manifest in many forms: delay, signal integrity degradation etc. When two signal lines are routed together, a capacitance exists between the lines. When one of the signals switch, it induces a change (glitch) on the other one. This relationship could change the second signal or possibly cause a delay in the transmission. Layout engineers work hard to ensure that these effects are reduced in chips for high performance and reliability.

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Over the years, the metal pitch has followed the trend of process improvement, which involves reduction of the transistor size to pack more units in a die. Unfortunately, the interconnect thickness has not followed the trend resulting to higher resistance per unit length. The effect of this is increase in delay as technology scales. Two major factors contributed to this: capacitance effects which have increased due to much nearer routing on-chip and resistance increases due to wire reduction. These combined factors pose limitation on system operating frequency.

There exist four main sources of interconnect noise in CMOS technologies: interconnect cross-capacitance, power supply, and mutual inductance and thermal noise sources. Interconnect cross-capacitance noise results from charge injected on a victim net due to switching on an aggressor net through a capacitance between them. Power supply noise is the spurious signal that appears on local voltage driver, which subsequently changes the signal value at the receiver.

Mutual inductance noise results when a voltage is induced on a signal line as a result of a changing magnetic field created when a signal switching causes current to flow through a loop. Finally, thermal noise emanates from joule heating along signal and power paths in circuits when current flows.

There is also a coupling (crosstalk) capacitance between two conductors. This capacitance introduces noise that degrades the signal integrity. It leads to rise on the spurious pulse on a neighboring wire, if it has a static value or causes delayed transition. Besides mutual capacitance, crosstalk is also determined by the ratio of the mutual to the sum of self and mutual capacitance (to ground).

The spacings between conductors in circuits decrease with technology downscaling. This increases the crosstalk and other sources of interconnection noise as the wires become more compact and closer to one another. This high circuit density contributes to long interconnections which could also increase crosstalk.

Crosstalk is a major source of timing uncertainty in circuits and it is more prevalent than process variations. Because of the presence of the capacitance, switching of the signals could result to lots of problems that could potentially result to functional degradation. For reduction of crosstalk, low permitivity dielectric material and signal de-synchronizations (non simultaneous switching of signals) are used.

Emerging techniques for interconnect noise reduction involve innovations in materials, circuits and layouts. Typical methods used include buffer insertion, wire sizing, wire spacing, shield insertion among. The ITRS 2005 forecasts increasing use of copper metallization and low-k dielectric insulators. The use of Cu over Al improves circuit propagation delay by reducing the interconnect resistance.

With Cu that has lower resistivity than Al, there is a gain on the delay. Further technology scaling continues to introduce more interconnect challenges despite the use of Cu. In the future, optimal techniques to scale interconnect systems with other circuit systems would be needed to reduce the impact of interconnect noise. New circuit and process techniques would be needed. Latch-up prevention and interconnect noise reduction using silicon silicon-on-insulator are expected to increase.

In conclusions, as CMOS technology continues to scale down, leakage currents and interconnection noise will become increasingly large due to the effects of electron tunnelling, short channel effects, coupling capacitance and other factors discussed in the paper.

Managing these factors by developing better circuits and processes would be vital to the continuous success of CMOS technologies in the semiconductor industry. This would require innovative control techniques and architectures in all aspects of CMOS design. Architectural innovation has already lead to renewed industrial interests in asynchronous integrated circuit which using clockless structure mitigate the effects of interconnect noise delays and other parasitics in circuits.

by Ndubuisi Ekekwe

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