Cadence Acquires Azuro, IC Design Power Optimization Specialist

Cadence Acquires Azuro, IC Design Power  Optimization Specialist

Cadence Designs Systems Inc.  a leader in IC design  has acquired Azuro – a company that  focuses on clock concurrent optimization technology that is billed as providing system on chip  designers with improved power, performance and area results.  Azuro has alerady joined a Cadence-sponsored software interoperability effort based on the Common Power Format last year.  The adapted  press release is available below.

 

Cadence Design Systems, Inc.,  a leader in global electronic design innovation, has announced it has acquired Azuro, Inc., a company that has pioneered a paradigm shift in the digital implementation and optimization of next-generation SoCs. Azuro offers unique clock concurrent optimization technology, also known as ccopt, which delivers superior capabilities for designers faced with increasing performance, power and area challenges. Specifically, ccopt technology has delivered significant quality of silicon (QoS) on high-speed processor designs in the areas of:

 

  • Power (clock tree power reduction up to 30 percent and total power improvements of up to 10 percent),
  • Performance (improvements of up to 100 MHz for a GHz design), and
  • Area (clock tree area reduction up to 30 percent)

The Azuro ccopt technology is experiencing rapid adoption by designers implementing high-speed embedded processors and complex SoCs. The technology uniquely integrates and merges core steps in the flow including timing-driven placement, useful-skew clock tree synthesis, incremental physical optimization, physical clock gating, and post-clock tree optimization.

 

“Traditional digital implementation flows are reaching their limits in their ability to meet the power, performance and area requirements of today’s SoC designs,” said Chi-Ping Hsu, senior vice president, research and development, Silicon Realization Group at Cadence. “Azuro has invented a truly disruptive technology that goes far beyond traditional, multi-step and iterative digital implementation flows and provides significant advantages for both today’s complex silicon and SoC designs, as well as advanced-node, next-generation SoCs. We welcome this team to Cadence, and its innovative technology to our award-winning Encounter Digital Implementation flow.”

 

“Realizing the growing challenges of increasingly complex SoCs, Azuro pioneered a fundamentally new approach to digital implementation that took into account the critical role of clocks in achieving power, performance, and area specs,” said Paul Cunningham, co-founder and CEO of Azuro. “Cadence has been aggressively advancing its digital implementation solution and shares our view of the innovation that is required to continue to help customers realize the next generation of design. We look forward to joining the Cadence team to bring a new generation of digital implementation to the industry.”

 

 

The increasing challenges of SoC design were outlined in the Cadence vision for the industry, called EDA360.  Cadence will offer the Azuro ccopt technology immediately as an upgrade add-on for Cadence EDI customers.

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