Among the different leakage currents in the nanometer CMS, the subthreshold and gate leakage are the most dominant. While the latter is mainly due to electron tunnelling from the gate to the substrate, the former is caused by many other factors. As a result, the leakage control techniques to be discussed will focus more on subthreshold currents. Over the years, many techniques have been developed to reduce the subthreshold currents in both the active and standby modes in order to minimize the total power consumption of CMOS circuits.
While the standby leakage currents are wasted currents when the circuit is in idle mode where no computation takes place, the active leakage currents are wasted current when the circuit is in use. Generally, reduction of leakage currents involves application of different device and circuit level techniques. At the device level, it involves controlling the doping profiles and physical dimensions of transistors while at the circuit level, it involves the manipulation of threshold voltage (Vth) and source biasing of the transistor.
A. Circuit Level Leakage Control Techniques
Registration for Tekedia Mini-MBA edition 9 (Sep 12 – Dec 3 2022) is ongoing. Register here. Cost is N60,000 or $140 for the 12-week program. Beat early bird for free books and other bonuses.
i) Multi Vth Techniques
This technique involves fabrication of two types of transistors, high Vth and low Vth transistors, on a chip. The high Vth is used to lower the subthreshold leakage current, while the low Vth is used to enhance performance through faster operation. Obtaining these different types of transistors is done through controlled channel doping, different oxide thickness, multiple channel lengths or multiple body biases. Notwithstanding, with technology scaling and continuous decrease in the supply voltage, the implementation of the high Vth transistor will become a major practical challenge.
Dual threshold method
In logic circuits, leakage current can be reduced by assigning higher Vth to devices in non-critical paths, while maintaining performance with low Vth in the critical paths. This technique is applicable to both standby and active mode leakage power dissipation control. It ensures that the circuit operates at a high speed and reduced power dissipation.
Multi-Threshold Voltage Method
This method uses a high Vth device to gate supply voltage from a low Vth logic block thereby creating a virtual power rail instead of directly connecting the block to the main power rail. The high Vth switches are used to disconnect the power supplies during the standby state, resulting in very low leakage currents set by the high Vth of the series logic block. In active mode operation, the high Vth transistors are switched on and the logic block, designed with low Vth, operates at fast speed.
This enables leakage current reduction via the high Vth and enhanced performance via the low Vth block. Alternatively, this system could be implemented with a high Vth NMOS transistor connected between the GND and the low Vth block. The NMOS transistor insertion is preferred to the PMOS since it has a lower ON-resistance at the same width and consequently can be sized smaller. The use of these transistors increases circuit delay and area. Besides, to retain data during standby mode, extra high Vth memory circuit is needed.
Variable Vth Method
This is a method mainly used to reduce standby leakage currents by using a triple well process where the device Vth is dynamically adjusted by biasing the body terminal. Through application of maximum reverse biasing during the standby mode, Vth is increased and the subthreshold leakage current minimized. In addition, this method could be applied in active mode operation to optimize circuit performance by dynamically tuning the Vth based on workload requirements. Through this tuning capability, the circuit is able to operate at the minimal active leakage power.
Dynamic Vth Method
This is a method used in active mode operation to control the leakage current in a circuit based on the desired frequency of operation. The frequency is dynamically adjusted through a back-gate bias in response to workload of a system. At low workload, increasing the Vth reduces the leakage power.
ii) Body Bias Control
Body biasing a transistor is an effective way of reducing both the active and standby leakage through its impact of increasing the threshold voltages of the MOS transistors. By applying a reverse body bias, the Vth is increased and subsequently reduces the subthreshold leakage currents. This could be done during standby mode by applying a strong negative bias to the NMOS bulk and connecting the PMOS bulks to the VDD rail. Body biasing is also used to minimize DIBL effect and Vth-Rolloff associated with SCE. The Variable Threshold CMOS technique described above utilises body biasing to improve circuit performance. It is important to note that the Vth is related by the square root of the bias voltage implying that a significant voltage level would be needed to raise the Vth. This could be a potential challenge in the UDSM where the supply has been severely scaled down.
iii) Minimum Leakage Vector Method
The fundamental concept in this technique is to force the combinational logic of the circuit into a low-leakage state during standby periods. This state enables the largest number of transistors to be turned off so as to reduce leakage and make use of multiple off transistors in stacks.
iv) Stack Effect-based Method
The “stacking effect” is the reduction in subthreshold current when multiple transistors connected in series (in a stack) are turned off. The transistor stacking increases the source bias of the upper transistors in the stack as well as lowers the gate-source voltage (Vgs) of these transistors. All these effects contribute to lower subthreshold leakage current in the circuit. Minimizing leakage through transistor stacking depends on the pattern of the input sequence during standby periods as it determines the number of OFF transistors in the stack.
Finding the low leakage input vector involves either a complete enumeration of the primary inputs or random search of the primary inputs. While the former is used for small circuits, the latter is applied for more complex circuits. The idea is to use the input vector to determine the combination that results to the least leakage current. When the input vector is obtained, the circuit is evaluated and if necessary, additional leakage control transistors are inserted in series at the non-critical paths to be turned OFF during the standby mode.
B. Device Level Leakage Control Techniques
Silicon-on-insulator (SOI): This is a non-bulk technology that builds transistors on top of insulating layer instead of a semiconductor substrate. Using insulating layer reduces parasitic capacitance, which results to higher operational speed and lower dynamic power dissipation in integrated circuits. Though the early SOI used crystals like sapphire, emerging technologies favour the use of silicon wafer, making it economically attractive. The ITRS 2005 projects the use of Ultra-thin body (UTB) SOI by 2008 to manage the increasing effects of leakage.
Double Gate MOSFET (DG-MOS): In traditional bulk and SOI devices, immunity from SCE like Vth-rolloff and DIBL requires increasing the channel doping to enable reduction of the depletion depth in the substrate. The inherent drawbacks to this approach are increased substrate-bias sensitivity and degraded subthreshold swing. By replacing the substrate with another gate to form a double gate MOSFET, short channel immunity is achieved with an ideal subthreshold swing.
Separation by Implantation of Oxygen (SIMOX): This is a more modern and elegant technique for making the SO1 structure by implanting heavy doses of oxygen directly into a silicon substrate. The wafer is then annealed at very high temperatures, which induces oxide growth below the wafer surface and pushes a top layer of silicon on the top. The resulting SOI consumes lesser power than the bulk technologies. Other methods used in device level control include retrograde doping and halo doping.
In addition to the two techniques discussed above, system and architectural level techniques are also used in leakage reduction. This technique could involve designing the system architecture so that it operates at low voltage. The underlining strategy is that when the system operates at low voltage, it reduces both the static and dynamic power consumption and consequently minimizes the leakage power. One of the ways of doing this is to design the system using pipeline architecture. With pipelining, it is possible to operate the system at lower voltage without performance degradation.
The penalty for this technique is extra hardware required for pipelining. Another method is threshold voltage hopping. This involves the use of software to dynamically control the threshold voltage of transistors based on the workloads of the system. By adjusting the threshold voltage in this way, high percentage power savings could be realised in a system. Furthermore, reduction in supply voltage is also a good technique to reduce leakage power. By lowering supply voltage, the source-drain voltage is reduced. This has the effect of minimizing DIBL, gate and subthreshold leakage currents.